Cita APA (7a ed.)
Liu, Y., Yang, F., & Feng, Z. (2025). Design of JESD204B Receiving Circuit in a 4Gsample/s 12Bit DAC. The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Conference Proceedings. https://doi.org/10.1109/ISSET66828.2025.11184945
Cita Chicago Style (17a ed.)
Liu, Yu, Feng Yang, y Zhenfu Feng. "Design of JESD204B Receiving Circuit in a 4Gsample/s 12Bit DAC." The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Conference Proceedings 2025. https://doi.org/10.1109/ISSET66828.2025.11184945.
Cita MLA (9a ed.)
Liu, Yu, et al. "Design of JESD204B Receiving Circuit in a 4Gsample/s 12Bit DAC." The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Conference Proceedings, 2025, https://doi.org/10.1109/ISSET66828.2025.11184945.
Precaución: Estas citas no son 100% exactas.