Design of an In-Memory Database Engine Using Intel Xeon Phi Coprocessors

Wedi'i Gadw mewn:
Manylion Llyfryddiaeth
Cyhoeddwyd yn:Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA) (2014), p. 1-7
Prif Awdur: Scherger, Michael
Cyhoeddwyd:
The Steering Committee of The World Congress in Computer Science, Computer Engineering and Applied Computing (WorldComp)
Mynediad Ar-lein:Citation/Abstract
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100 1 |a Scherger, Michael 
245 1 |a Design of an In-Memory Database Engine Using Intel Xeon Phi Coprocessors 
260 |b The Steering Committee of The World Congress in Computer Science, Computer Engineering and Applied Computing (WorldComp)  |c 2014 
513 |a Feature 
520 3 |a   This research presents the design and initial implementation of a database engine using an Intel Xeon Phi co-processor. The many integrated cores (MIC) of the Xeon Phi make this hardware accelerator a natural computing platform for an in-memory database engine or server. The database tables reside in the memory space of the MIC thus supporting fast in-memory database applications. This achieved by developing a coalescing parallel memory manager to allocate parallel variables in the same manner that fields are created in a table using a SQL CREATE TABLE command. The SQL interface was created using a database driver toolkit that provides an interface to the Xeon Phi server and client application. Once the basic framework was established, the algorithms for SQL select, insert, update, delete, and join were created to manipulate database information in the memory of the Xeon Phi. 
773 0 |t Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA)  |g (2014), p. 1-7 
786 0 |d ProQuest  |t Advanced Technologies & Aerospace Database 
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