An Operational Framework for Specifying Memory Models using Instantaneous Instruction Execution
Պահպանված է:
| Հրատարակված է: | arXiv.org (May 16, 2017), p. n/a |
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| Հիմնական հեղինակ: | |
| Այլ հեղինակներ: | , |
| Հրապարակվել է: |
Cornell University Library, arXiv.org
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| Խորագրեր: | |
| Առցանց հասանելիություն: | Citation/Abstract Full text outside of ProQuest |
| Ցուցիչներ: |
Չկան պիտակներ, Եղեք առաջինը, ով նշում է այս գրառումը!
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| Համառոտագրություն: | There has been great progress recently in formally specifying the memory model of microprocessors like ARM and POWER. These specifications are, however, too complicated for reasoning about program behaviors, verifying compilers etc., because they involve microarchitectural details like the reorder buffer (ROB), partial and speculative execution, instruction replay on speculation failure, etc. In this paper we present a new Instantaneous Instruction Execution (I2E) framework which allows us to specify weak memory models in the same style as SC and TSO. Each instruction in I2E is executed instantaneously and in-order such that the state of the processor is always correct. The effect of instruction reordering is captured by the way data is moved between the processors and the memory non-deterministically, using three conceptual devices: invalidation buffers, timestamps and dynamic store buffers. We prove that I2E models capture the behaviors of modern microarchitectures and cache-coherent memory systems accurately, thus eliminating the need to think about microarchitectural details. |
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| ISSN: | 2331-8422 |
| Աղբյուր: | Engineering Database |