ASIC verification software automates partitioning

Guardat en:
Dades bibliogràfiques
Publicat a:Electronic Design vol. 49, no. 18 (Sep 3, 2001), p. 34.
Autor principal: Maliniak, David
Publicat:
Endeavor Business Media
Matèries:
Accés en línia:Citation/Abstract
Full Text + Graphics
Full Text - PDF
Etiquetes: Afegir etiqueta
Sense etiquetes, Sigues el primer a etiquetar aquest registre!

MARC

LEADER 00000nab a2200000uu 4500
001 221035881
003 UK-CbPIL
022 |a 0013-4872 
022 |a 1944-9550 
035 |a 221035881 
045 0 |b d20010903 
084 |a 27955  |2 nlm 
100 1 |a Maliniak, David 
245 1 |a ASIC verification software automates partitioning 
260 |b Endeavor Business Media  |c Sep 3, 2001 
513 |a Feature 
520 3 |a Earlier versions of Certify incorporated the ability to recognize gated clock tree structures in an ASIC and convert them to dock enables in an FPGA. In addition to the logic gate elements previously recognized in the clock tree, the tool can now detect clock trees with inferred and instantiated memories and latches, instantiated registers, shift registers, state machines, and counters. This eliminates the time-consuming task of manually converting gated-- clock elements. 
610 4 |a Synplicity Inc 
651 4 |a United States--US 
653 |a Electronic design automation 
653 |a Software packages 
653 |a Automation 
653 |a Product introduction 
653 |a Design 
653 |a Designers 
773 0 |t Electronic Design  |g vol. 49, no. 18 (Sep 3, 2001), p. 34. 
786 0 |d ProQuest  |t Science Database 
856 4 1 |3 Citation/Abstract  |u https://www.proquest.com/docview/221035881/abstract/embedded/J7RWLIQ9I3C9JK51?source=fedsrch 
856 4 0 |3 Full Text + Graphics  |u https://www.proquest.com/docview/221035881/fulltextwithgraphics/embedded/J7RWLIQ9I3C9JK51?source=fedsrch 
856 4 0 |3 Full Text - PDF  |u https://www.proquest.com/docview/221035881/fulltextPDF/embedded/J7RWLIQ9I3C9JK51?source=fedsrch