Verification methods for complex-functional blocks in CAD for chips deep submicron design standards
Պահպանված է:
| Հրատարակված է: | E3S Web of Conferences vol. 376 (2023), p. n/a |
|---|---|
| Հիմնական հեղինակ: | |
| Այլ հեղինակներ: | , , |
| Հրապարակվել է: |
EDP Sciences
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| Խորագրեր: | |
| Առցանց հասանելիություն: | Citation/Abstract Full Text - PDF |
| Ցուցիչներ: |
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| 022 | |a 2555-0403 | ||
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| 024 | 7 | |a 10.1051/e3sconf/202337601090 |2 doi | |
| 035 | |a 2793408499 | ||
| 045 | 2 | |b d20230101 |b d20231231 | |
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| 100 | 1 | |a Zolnikov, Vladimir | |
| 245 | 1 | |a Verification methods for complex-functional blocks in CAD for chips deep submicron design standards | |
| 260 | |b EDP Sciences |c 2023 | ||
| 513 | |a Conference Proceedings | ||
| 520 | 3 | |a The article discusses the design stages of very large-scale integrated circuits (VLSI) and the features of the procedure for verifying complex-functional VLSI blocks. The main approaches to microcircuit verification procedures are analyzed to minimize the duration of verification cycles. In practice, a combination of several approaches to verification is usually used. | |
| 651 | 4 | |a Russia | |
| 653 | |a Very large scale integration | ||
| 653 | |a Design standards | ||
| 653 | |a Verification | ||
| 653 | |a Circuit design | ||
| 653 | |a Integrated circuits | ||
| 653 | |a Software | ||
| 653 | |a Semiconductors | ||
| 653 | |a Environmental | ||
| 700 | 1 | |a Zolnikov, Konstantin | |
| 700 | 1 | |a Ilina, Nadezhda | |
| 700 | 1 | |a Grabovy, Kirill | |
| 773 | 0 | |t E3S Web of Conferences |g vol. 376 (2023), p. n/a | |
| 786 | 0 | |d ProQuest |t Engineering Database | |
| 856 | 4 | 1 | |3 Citation/Abstract |u https://www.proquest.com/docview/2793408499/abstract/embedded/BH75TPHOCCPB476R?source=fedsrch |
| 856 | 4 | 0 | |3 Full Text - PDF |u https://www.proquest.com/docview/2793408499/fulltextPDF/embedded/BH75TPHOCCPB476R?source=fedsrch |