DeTRAP: RISC-V Return Address Protection With Debug Triggers

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Publicat a:arXiv.org (Aug 30, 2024), p. n/a
Autor principal: Richter, Isaac
Altres autors: Zhou, Jie, Criswell, John
Publicat:
Cornell University Library, arXiv.org
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Accés en línia:Citation/Abstract
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022 |a 2331-8422 
035 |a 3099944773 
045 0 |b d20240830 
100 1 |a Richter, Isaac 
245 1 |a DeTRAP: RISC-V Return Address Protection With Debug Triggers 
260 |b Cornell University Library, arXiv.org  |c Aug 30, 2024 
513 |a Working Paper 
520 3 |a Modern microcontroller software is often written in C/C++ and suffers from control-flow hijacking vulnerabilities. Previous mitigations suffer from high performance and memory overheads and require either the presence of memory protection hardware or sophisticated program analysis in the compiler. This paper presents DeTRAP (Debug Trigger Return Address Protection). DeTRAP utilizes a full implementation of the RISC-V debug hardware specification to provide a write-protected shadow stack for return addresses. Unlike previous work, DeTRAP requires no memory protection hardware and only minor changes to the compiler toolchain. We tested DeTRAP on an FPGA running a 32-bit RISC-V microcontroller core and found average execution time overheads to be between 0.5% and 1.9% on evaluated benchmark suites with code size overheads averaging 7.9% or less. 
653 |a Microcontrollers 
653 |a Program verification (computers) 
653 |a Compilers 
653 |a Hardware 
700 1 |a Zhou, Jie 
700 1 |a Criswell, John 
773 0 |t arXiv.org  |g (Aug 30, 2024), p. n/a 
786 0 |d ProQuest  |t Engineering Database 
856 4 1 |3 Citation/Abstract  |u https://www.proquest.com/docview/3099944773/abstract/embedded/6A8EOT78XXH2IG52?source=fedsrch 
856 4 0 |3 Full text outside of ProQuest  |u http://arxiv.org/abs/2408.17248