Distributed Binary Optimization with In-Memory Computing: An Application for the SAT Problem

Tallennettuna:
Bibliografiset tiedot
Julkaisussa:arXiv.org (Dec 3, 2024), p. n/a
Päätekijä: Zhang, Xiangyi
Muut tekijät: Böhm, Fabian, Valiante, Elisabetta, Noori, Moslem, Thomas Van Vaerenbergh, Chan-Woo, Yang, Pedretti, Giacomo, Mohseni, Masoud, Beausoleil, Raymond, Rozada, Ignacio
Julkaistu:
Cornell University Library, arXiv.org
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Linkit:Citation/Abstract
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LEADER 00000nab a2200000uu 4500
001 3106245815
003 UK-CbPIL
022 |a 2331-8422 
035 |a 3106245815 
045 0 |b d20241203 
100 1 |a Zhang, Xiangyi 
245 1 |a Distributed Binary Optimization with In-Memory Computing: An Application for the SAT Problem 
260 |b Cornell University Library, arXiv.org  |c Dec 3, 2024 
513 |a Working Paper 
520 3 |a In-memory computing (IMC) has been shown to be a promising approach for solving binary optimization problems while significantly reducing energy and latency. Building on the advantages of parallel computation, we propose an IMC-compatible parallelism framework inspired by parallel tempering (PT), enabling cross-replica communication to improve the performance of IMC solvers. This framework enables an IMC solver not only to improve performance beyond what can be achieved through parallelization, but also affords greater flexibility for the search process with low hardware overhead. We justify that the framework can be applied to almost any IMC solver. We demonstrate the effectiveness of the framework for the Boolean satisfiability (SAT) problem, using the WalkSAT heuristic as a proxy for existing IMC solvers. The resulting PT-inspired cooperative WalkSAT (PTIC-WalkSAT) algorithm outperforms the traditional WalkSAT heuristic in terms of the iterations-to-solution in 76.3% of the tested problem instances and its na\"ive parallel variant (PA-WalkSAT) does so in 68.4% of the instances. An estimate of the energy overhead of the PTIC framework for two hardware accelerator architectures indicates that in both cases the overhead of running the PTIC framework would be less than 1% of the total energy required to run each accelerator. 
653 |a Search process 
653 |a Heuristic 
653 |a Parallel processing 
653 |a Solvers 
653 |a Algorithms 
653 |a Performance enhancement 
653 |a Computation 
653 |a Hardware 
653 |a Distributed memory 
653 |a Optimization 
700 1 |a Böhm, Fabian 
700 1 |a Valiante, Elisabetta 
700 1 |a Noori, Moslem 
700 1 |a Thomas Van Vaerenbergh 
700 1 |a Chan-Woo, Yang 
700 1 |a Pedretti, Giacomo 
700 1 |a Mohseni, Masoud 
700 1 |a Beausoleil, Raymond 
700 1 |a Rozada, Ignacio 
773 0 |t arXiv.org  |g (Dec 3, 2024), p. n/a 
786 0 |d ProQuest  |t Engineering Database 
856 4 1 |3 Citation/Abstract  |u https://www.proquest.com/docview/3106245815/abstract/embedded/ZKJTFFSVAI7CB62C?source=fedsrch 
856 4 0 |3 Full text outside of ProQuest  |u http://arxiv.org/abs/2409.09152