A Comprehensive Simulation Framework for CXL Disaggregated Memory

সংরক্ষণ করুন:

গ্রন্থ-পঞ্জীর বিবরন
প্রকাশিত:	arXiv.org (Dec 4, 2024), p. n/a
প্রধান লেখক:	Wang, Yanjing
অন্যান্য লেখক:	Wu, Lizhou, Hong, Wentao, Yang, Ou, Wang, Zicong, Gao, Sunfeng, Zhang, Jie, Ma, Sheng, Dong, Dezun, Qi, Xingyun, Lai, Mingche, Xiao, Nong
প্রকাশিত:	Cornell University Library, arXiv.org
বিষয়গুলি:	Simulation Performance enhancement Computer memory Field programmable gate arrays Control systems design Resource utilization Bandwidths Application specific integrated circuits Device driver programs
অনলাইন ব্যবহার করুন:	Citation/Abstract Full text outside of ProQuest
ট্যাগগুলো:	ট্যাগ যুক্ত করুন কোনো ট্যাগ নেই, প্রথমজন হিসাবে ট্যাগ করুন!

বিবরন
সার সংক্ষেপ:	Compute eXpress Link (CXL) is a pivotal technology for memory disaggregation in future heterogeneous computing systems, enabling on-demand memory expansion and improved resource utilization. Despite its potential, CXL is in its early stages with limited market products, highlighting the need for a reliable system-level simulation tool. This paper introduces CXL-DMSim, an open-source, high-fidelity full-system simulator for CXL disaggregated memory systems, comparable in speed to gem5. CXL-DMSim includes a flexible CXL memory expander model, device driver, and support for CXL\.io and CXL\.mem protocols. It supports both app-managed and kernel-managed modes, with the latter featuring a NUMA-compatible mechanism. Rigorous verification against real hardware testbeds with FPGA-based and ASIC-based CXL memory prototypes confirms CXL-DMSim's accuracy, with an average simulation error of 4.1%. Benchmark results using LMbench and STREAM indicate that CXL-FPGA memory has approximately ~2.88x higher latency than local DDR, while CXL-ASIC latency is about ~2.18x. CXL-FPGA achieves 45-69% of local DDR's memory bandwidth, and CXL-ASIC reaches 82-83%. The performance of CXL memory is significantly more sensitive to Rd/Wr patterns than local DDR, with optimal bandwidth at a 74%:26% ratio rather than 50%:50% due to the current CXL+DDR controller design. The study also shows that CXL memory can markedly enhance the performance of memory-intensive applications, with the most improvement seen in Viper (~23x) and in bandwidth-sensitive scenarios like MERCI (16%). CXL-DMSim's observability and expandability are demonstrated through detailed case studies, showcasing its potential for research on future CXL-interconnected hybrid memory pools.
আইএসএসএন:	2331-8422
সম্পদ:	Engineering Database