Enhanced Resolution and Accuracy in Software Defined Radio Applications Using a SAR ADC with Integrated ECC Mechanism and Dual-Stage SAR Architecture
保存先:
| 出版年: | SN Computer Science vol. 5, no. 8 (Dec 2024), p. 1133 |
|---|---|
| 出版事項: |
Springer Nature B.V.
|
| 主題: | |
| オンライン･アクセス: | Citation/Abstract Full Text Full Text - PDF |
| タグ: |
タグなし, このレコードへの初めてのタグを付けませんか!
|
| 抄録: | Article presents a novel architecture for a Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) that incorporates an Error Correction Code (ECC) mechanism to significantly improve resolution and accuracy. The proposed design employs a dual-stage SAR approach, consisting of a coarse stage for initial approximation and a fine stage for refinement. Sample and Hold(S&H) circuit, Digital-to-Analog(DAC) Converter, Comparator, and SAR logic are integrated to complete the conversion process.The ECC mechanism enhances the reliability of the digital output by detecting and correcting single-bit errors, ensuring the integrity of the signal. This is particularly crucial for Software Defined Radio (SDR) applications demanding high-speed and high-accuracy conversions. Simulation results demonstrate that the proposed architecture surpasses traditional SAR ADCs in terms of resolution, speed, and accuracy. Its potential applications extend beyond SDR to medical devices, instrumentation, and communication systems requiring high reliability and precision, making it a versatile solution for modern electronic systems. |
|---|---|
| ISSN: | 2662-995X 2661-8907 |
| DOI: | 10.1007/s42979-024-03512-x |
| ソース: | Advanced Technologies & Aerospace Database |