Integrated probabilistic computer using voltage-controlled magnetic tunnel junctions as its entropy source
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| 發表在: | arXiv.org (Dec 11, 2024), p. n/a |
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| 主要作者: | |
| 其他作者: | , , , , , , , |
| 出版: |
Cornell University Library, arXiv.org
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| 主題: | |
| 在線閱讀: | Citation/Abstract Full text outside of ProQuest |
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| Resumen: | Probabilistic Ising machines (PIMs) provide a path to solving many computationally hard problems more efficiently than deterministic algorithms on von Neumann computers. Stochastic magnetic tunnel junctions (S-MTJs), which are engineered to be thermally unstable, show promise as entropy sources in PIMs. However, scaling up S-MTJ-PIMs is challenging, as it requires fine control of a small magnetic energy barrier across large numbers of devices. In addition, non-spintronic components of S-MTJ-PIMs to date have been primarily realized using general-purpose processors or field-programmable gate arrays. Reaching the ultimate performance of spintronic PIMs, however, requires co-designed application-specific integrated circuits (ASICs), combining CMOS with spintronic entropy sources. Here we demonstrate an ASIC in 130 nm foundry CMOS, which implements integer factorization as a representative hard optimization problem, using PIM-based invertible logic gates realized with 1143 probabilistic bits. The ASIC uses stochastic bit sequences read from an adjacent voltage-controlled (V-) MTJ chip. The V-MTJs are designed to be thermally stable in the absence of voltage, and generate random bits on-demand in response to 10 ns pulses using the voltage-controlled magnetic anisotropy effect. We experimentally demonstrate the chip's functionality and provide projections for designs in advanced nodes, illustrating a path to millions of probabilistic bits on a single CMOS+V-MTJ chip. |
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| ISSN: | 2331-8422 |
| Fuente: | Engineering Database |