Εξώφυλλο

A Hierarchical Cache Architecture-Oriented Cache Management Scheme for Information-Centric Networking

Αποθηκεύτηκε σε:
Εκδόθηκε σε:Future Internet vol. 17, no. 1 (2025), p. 17
Κύριος συγγραφέας: Chao, Yichao
Άλλοι συγγραφείς: Han, Rui
Έκδοση:
MDPI AG
Θέματα:
Solid state devices
Replacement
Data transfer (computers)
Dynamic random access memory
Data storage
Computer architecture
Costs
Popularity
Traffic capacity
Memory management
Network latency
Διαθέσιμο Online:Citation/Abstract
Full Text + Graphics
Full Text - PDF
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045 2 |b d20250101  |b d20251231 
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100 1 |a Chao, Yichao  |u National Network New Media Engineering Research Center, Institute of Acoustics, Chinese Academy of Sciences, No. 21, North Fourth Ring Road, Haidian District, Beijing 100190, China; School of Electronic, Electrical and Communication Engineering, University of Chinese Academy of Sciences, No. 19(A), Yuquan Road, Shijingshan District, Beijing 100049, China 
245 1 |a A Hierarchical Cache Architecture-Oriented Cache Management Scheme for Information-Centric Networking 
260 |b MDPI AG  |c 2025 
513 |a Journal Article 
520 3 |a Information-Centric Networking (ICN) typically utilizes DRAM (Dynamic Random Access Memory) to build in-network cache components due to its high data transfer rate and low latency. However, DRAM faces significant limitations in terms of cost and capacity, making it challenging to meet the growing demands for cache scalability required by increasing Internet traffic. Combining high-speed but expensive memory (e.g., DRAM) with large-capacity, low-cost storage (e.g., SSD) to construct a hierarchical cache architecture has emerged as an effective solution to this problem. However, how to perform efficient cache management in such architectures to realize the expected cache performance remains challenging. This paper proposes a cache management scheme for hierarchical cache architectures in ICN, which introduces a differentiated replica replacement policy to accommodate the varying request access patterns at different cache layers, thereby enhancing overall cache performance. Additionally, a probabilistic insertion-based SSD cache admission filtering mechanism is designed to control the SSD write load, addressing the issue of balancing SSD lifespan and space utilization. Extensive simulation results demonstrate that the proposed scheme exhibits superior cache performance and lower SSD write load under various workloads and replica placement strategies, highlighting its broad applicability to different application scenarios. Additionally, it maintains stable performance improvements across different cache capacity settings, further reflecting its good scalability. 
653 |a Solid state devices 
653 |a Replacement 
653 |a Data transfer (computers) 
653 |a Dynamic random access memory 
653 |a Data storage 
653 |a Computer architecture 
653 |a Costs 
653 |a Popularity 
653 |a Traffic capacity 
653 |a Memory management 
653 |a Network latency 
700 1 |a Han, Rui  |u National Network New Media Engineering Research Center, Institute of Acoustics, Chinese Academy of Sciences, No. 21, North Fourth Ring Road, Haidian District, Beijing 100190, China; School of Electronic, Electrical and Communication Engineering, University of Chinese Academy of Sciences, No. 19(A), Yuquan Road, Shijingshan District, Beijing 100049, China 
773 0 |t Future Internet  |g vol. 17, no. 1 (2025), p. 17 
786 0 |d ProQuest  |t ABI/INFORM Global 
856 4 1 |3 Citation/Abstract  |u https://www.proquest.com/docview/3159471017/abstract/embedded/7BTGNMKEMPT1V9Z2?source=fedsrch 
856 4 0 |3 Full Text + Graphics  |u https://www.proquest.com/docview/3159471017/fulltextwithgraphics/embedded/7BTGNMKEMPT1V9Z2?source=fedsrch 
856 4 0 |3 Full Text - PDF  |u https://www.proquest.com/docview/3159471017/fulltextPDF/embedded/7BTGNMKEMPT1V9Z2?source=fedsrch