Security Aware CAD Frameworks: From RTL to Layout
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| Հրատարակված է: | ProQuest Dissertations and Theses (2025) |
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ProQuest Dissertations & Theses
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| Համառոտագրություն: | The landscape of secure integrated circuit (IC) design faces mounting challenges due to the increasing reliance on third-party foundries and complex supply chains. This has introduced various security threats, ranging from intellectual property (IP) theft to physical attacks such as probing, side-channel analysis, and the insertion of malicious components known as hardware Trojans. The protection of the chip design is considered one of the most fundamental challenges in the ever-increasing field of hardware security. Although some techniques and proof-of-concept implementations have shown promise against specific threat models, they often carry substantial overhead or are otherwise impractical in real-world scenarios.This thesis aims to advance the protection of IC design using computer-aided design (CAD) frameworks. Toward that end, this thesis proposed innovative approaches that prioritize security alongside traditional metrics such as power, performance, and area (PPA).Initially, the evaluation of embedded field programmable gate array (eFPGA) architecture for redaction provides a promising solution for concealing sensitive design portions and enabling the secure deployment of critical IPs in untrusted environments. Only authorized end-users can restore full functionality via a specific bitstream by redacting essential parts of a digital design and loading them onto a reconfigurable eFPGA. Yet, the effectiveness of eFPGA-based redaction depends on factors like area and timing overheads, which vary significantly across different FPGA architectures. Our work delves into these trade-offs, evaluating how distinct eFPGA configurations impact PPA and resilience against reverse-engineering (RE) attacks, particularly boolean satisfiability (SAT) based bitstream recovery. Next, our DEFense framework offers a CAD solution for proactive threat mitigation during the IC design stage. It targets a variety of threats, such as hardware Trojans, probing, and crosstalk, through an extensible framework that allows holistic assessment and iterative security reinforcement within commercial CAD flows. By prioritizing security alongside PPA, DEFense equips designers with tools to safeguard active devices and wiring in IC layouts without compromising design quality.Next, this thesis explores power side-channel (PSC) threats, which exploit static and dynamic power characteristics to leak information and pose additional risks to cryptographic ICs. Advanced technology nodes exacerbate these vulnerabilities, yet mitigating such threats remains challenging due to significant performance and area costs. We study the role of standard cells within different threshold-voltage (VT) configurations, finding that specific VT tuning can enhance the resilience of ICs against PSC attacks. We also proposed a lightweight countermeasure (LiCSPA) against static PSC, which is based on the use of different VT cells with high resilience to the attacks and minimal overhead.Additionally, to address these vulnerabilities holistically, the ASCENT framework redefines traditional PPA-optimized logic synthesis with a “security-first” approach. Leveraging learning-based optimization Monte Carlo Tree Search (MCTS), ASCENT dramatically accelerates PSC countermeasure evaluation, enabling an extensive search of the design space.Overall, this thesis advances state-of-the-art IC protection: (i) eFPGA redaction for IP protection, (ii) DEFense for IC layout security, and (iii) identifying and exploring the role of VT cells for PSC-resistant synthesis, LiCSPA and ASCENT. By balancing security with PPA objectives, this thesis proposes a suite of CAD frameworks for more robust defenses against evolving threats in a rapidly changing semiconductor landscape. |
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| ISBN: | 9798315745402 |
| Աղբյուր: | ProQuest Dissertations & Theses Global |