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Dual-Bit FeFET for enhanced storage and endurance

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Publicado en:NPJ Unconventional Computing vol. 2, no. 1 (Dec 2025), p. 16
Autor principal: Benkhelifa, Mahdi
Otros Autores: Thomann, Simon, Ni, Kai, Amrouch, Hussam
Publicado:
Nature Publishing Group
Materias:
Pulse duration
Design
Storage capacity
Computer memory
Ferroelectricity
Semiconductor devices
Arrays
Voltage pulses
Field effect transistors
Ferroelectric materials
Acceso en línea:Citation/Abstract
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Full Text - PDF
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024 7 |a 10.1038/s44335-025-00030-8  |2 doi 
035 |a 3226853416 
045 2 |b d20251201  |b d20251231 
100 1 |a Benkhelifa, Mahdi  |u Munich Institute of Robotics and Machine Intelligence, Technical University of Munich; TUM School of Computation, Information and Technology, Chair of AI Processor Design, Munich, Germany (GRID:grid.6936.a) (ISNI:0000 0001 2322 2966) 
245 1 |a Dual-Bit FeFET for enhanced storage and endurance 
260 |b Nature Publishing Group  |c Dec 2025 
513 |a Journal Article 
520 3 |a This work presents a novel Dual-Bit Ferroelectric Field-Effect Transistor (FeFET) structure that enables localized control of the ferroelectric (FE) layer through a segmented metal gate. This design allows for independent domain switching in distinct regions of the FE material, enabling the memory cell to store two discrete bits while maintaining robust read margins. Crucially, this approach eliminates the need for complex pulsing schemes, such as staircase write voltage pulses, which are typically required for multi-level cell (MLC) FeFETs. We demonstrate the functionality of this device through comprehensive TCAD simulations of read and write operations, considering both process variations and stochastic domain switching behavior. The device achieves a large memory window of 1.61 V even with reduced Program/Erase (P/E) voltages of ±3.3 V and a pulse duration of 1 μs–considerably improving efficiency and endurance. In contrast, conventional FeFETs require higher write voltages (i.e., ±4 V for 10 μs), which accelerate the underlying defect and trap generation, resulting in limited endurance. Our dual-bit design holds the potential for extending the endurance of FeFET-based crossbar arrays, which are crucial for AI accelerators. By effectively doubling the storage capacity, this approach reduces the frequency of weight reprogramming, addressing a key limitation in existing compute-in-memory architectures. 
653 |a Pulse duration 
653 |a Design 
653 |a Storage capacity 
653 |a Computer memory 
653 |a Ferroelectricity 
653 |a Semiconductor devices 
653 |a Arrays 
653 |a Voltage pulses 
653 |a Field effect transistors 
653 |a Ferroelectric materials 
700 1 |a Thomann, Simon  |u Munich Institute of Robotics and Machine Intelligence, Technical University of Munich; TUM School of Computation, Information and Technology, Chair of AI Processor Design, Munich, Germany (GRID:grid.6936.a) (ISNI:0000 0001 2322 2966) 
700 1 |a Ni, Kai  |u University of Notre Dame, Department of Electrical Engineering, Notre Dame, USA (GRID:grid.131063.6) (ISNI:0000 0001 2168 0066) 
700 1 |a Amrouch, Hussam  |u Munich Institute of Robotics and Machine Intelligence, Technical University of Munich; TUM School of Computation, Information and Technology, Chair of AI Processor Design, Munich, Germany (GRID:grid.6936.a) (ISNI:0000 0001 2322 2966) 
773 0 |t NPJ Unconventional Computing  |g vol. 2, no. 1 (Dec 2025), p. 16 
786 0 |d ProQuest  |t Advanced Technologies & Aerospace Database 
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856 4 0 |3 Full Text - PDF  |u https://www.proquest.com/docview/3226853416/fulltextPDF/embedded/7BTGNMKEMPT1V9Z2?source=fedsrch