Architectures for Heterogeneous Memory and Storage Hierarchies in Modern Datacenters
Salvato in:
| Pubblicato in: | ProQuest Dissertations and Theses (2025) |
|---|---|
| Autore principale: | |
| Pubblicazione: |
ProQuest Dissertations & Theses
|
| Soggetti: | |
| Accesso online: | Citation/Abstract Full Text - PDF |
| Tags: |
Nessun Tag, puoi essere il primo ad aggiungerne!!
|
MARC
| LEADER | 00000nab a2200000uu 4500 | ||
|---|---|---|---|
| 001 | 3255239163 | ||
| 003 | UK-CbPIL | ||
| 020 | |a 9798293889785 | ||
| 035 | |a 3255239163 | ||
| 045 | 2 | |b d20250101 |b d20251231 | |
| 084 | |a 66569 |2 nlm | ||
| 100 | 1 | |a Sudarshan, Sujay Yadalam | |
| 245 | 1 | |a Architectures for Heterogeneous Memory and Storage Hierarchies in Modern Datacenters | |
| 260 | |b ProQuest Dissertations & Theses |c 2025 | ||
| 513 | |a Dissertation/Thesis | ||
| 520 | 3 | |a Datacenters are increasingly adopting heterogeneous memory and storage hierarchies to meet the demands of modern data-intensive workloads. Datacenter hierarchies include not just DRAM and disks but also new technologies such as Non-Volatile Memory (NVM), CXL-attached memory and ultra-low-latency SSDs. Traditional interfaces and system software fall short in fully utilizing the potential of these new devices. This dissertation tackles some of the challenges in integrating these new memory and storage technologies into existing hierarchies by rethinking the system software that manages them and/or the hardware interface. These new interfaces, system policies and runtime systems help applications exploit fully the potential of these devices.First, I introduce ASAP, a speculative persistence model for byte-addressable NVM that preserves crash consistency without stalling normal execution. ASAP uses a hardware persist buffer to track and persist data to NVM ASAP eagerly flushes data and speculatively updates the memory for high performance. To handle the occasional crash, it stores minimal recovery data in the memory controller caches. Simulation experiments show that ASAP achieves 2.3x average speedup over existing systems and performs within 4% of an ideal instantly-persistent system.Second, I present BypassD, a novel I/O architecture that eliminates software overheads in the critical path of I/O operations to modern ultra-low-latency SSDs while also ensuring that multiple applications can share the device safely. BypassD virtualizes SSD block addresses and relies on the IOMMU to perform translation and permission checks. BypassD reduces I/O latencies by 40% and improves performance of real-life workloads such as WiredTiger by 20%.Third, I develop ARMS - Adaptive and Robust Memory tiering System - that overcomes the limitations of existing tiering systems by eliminating static thresholds. ARMS combines dual-horizon moving-average hotness scoring, cost-benefit-aware migration, and bandwidth-aware batched transfers to adapt online to workload and platform changes, matching tuned heuristics (within 3%) while outperforming state-of-the-art systems by 1.26x-2.3x, without any per-workload tuning. | |
| 653 | |a Computer science | ||
| 653 | |a Computer engineering | ||
| 653 | |a Information technology | ||
| 773 | 0 | |t ProQuest Dissertations and Theses |g (2025) | |
| 786 | 0 | |d ProQuest |t ProQuest Dissertations & Theses Global | |
| 856 | 4 | 1 | |3 Citation/Abstract |u https://www.proquest.com/docview/3255239163/abstract/embedded/Y2VX53961LHR7RE6?source=fedsrch |
| 856 | 4 | 0 | |3 Full Text - PDF |u https://www.proquest.com/docview/3255239163/fulltextPDF/embedded/Y2VX53961LHR7RE6?source=fedsrch |