Energy aware computer vision algorithm deployment on heterogeneous architectures

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Publicat a:Discover Electronics vol. 2, no. 1 (Dec 2025), p. 42
Autor principal: Ali, Teymoor
Altres autors: Bhowmik, Deepayan, Nicol, Robert
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Springer Nature B.V.
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024 7 |a 10.1007/s44291-025-00078-7  |2 doi 
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045 2 |b d20251201  |b d20251231 
100 1 |a Ali, Teymoor  |u University of Strathclyde, Department of Electronic and Electrical Engineering, Glasgow, UK (GRID:grid.11984.35) (ISNI:0000 0001 2113 8138); STMicroelectronics (R&D) Ltd., Sensor Technology Group, Imaging Division, Edinburgh, UK (GRID:grid.11984.35) 
245 1 |a Energy aware computer vision algorithm deployment on heterogeneous architectures 
260 |b Springer Nature B.V.  |c Dec 2025 
513 |a Journal Article 
520 3 |a Computer vision algorithms, specifically convolutional neural networks (CNNs) and feature extraction algorithms, have become increasingly pervasive in many vision tasks. As algorithm complexity grows, it raises computational and memory requirements, which poses a challenge to embedded vision systems with limited resources. Heterogeneous architectures have recently gained momentum as a new path forward for energy efficiency and faster computation, as they allow for the effective utilisation of various processing units, such as Central Processing Unit (CPU), Graphics Processing Unit (GPU), and Field Programmable Gate Array (FPGA), which are tightly integrated into a single platform to enhance system performance. However, partitioning algorithms over each accelerator requires careful consideration of hardware limitations and scheduling. We propose two low-high power heterogeneous systems and a method of partitioning CNNs and a feature extraction algorithm (SIFT) onto the hardware. We benchmark feature detection and image classification algorithms on heterogeneous systems and their discrete accelerator counterparts. We demonstrate that both systems outperform FPGA/GPU-only accelerators. Experimental results show that for the SIFT algorithm, there is 18% runtime improvement over the GPU. In the case of MobilenetV2 and ResNet18 networks, the high power system achieves 17.75%/5.55% runtime and 6.25%/2.08% energy improvements respectively, against their discrete counterparts. The low-power system achieves 6.32%/16.21% runtime and 7.32%/3.27% energy savings. The results show that effective partitioning and scheduling of imaging algorithms on heterogeneous systems is a step towards better efficiency over traditional FPGA/GPU-only accelerators. 
653 |a Feature extraction 
653 |a Central processing units--CPUs 
653 |a Deep learning 
653 |a Hardware 
653 |a Vision systems 
653 |a Communication 
653 |a Bandwidths 
653 |a Artificial neural networks 
653 |a Real time 
653 |a Task complexity 
653 |a Computer vision 
653 |a Field programmable gate arrays 
653 |a Energy consumption 
653 |a Partitioning 
653 |a Accelerators 
653 |a Scheduling 
653 |a Embedded systems 
653 |a Graphics processing units 
653 |a Neural networks 
653 |a Power management 
653 |a Image classification 
653 |a Design 
653 |a Algorithms 
653 |a Energy efficiency 
653 |a Run time (computers) 
700 1 |a Bhowmik, Deepayan  |u Newcastle University, School of Computing, Newcastle upon Tyne, UK (GRID:grid.1006.7) (ISNI:0000 0001 0462 7212) 
700 1 |a Nicol, Robert  |u STMicroelectronics (R&D) Ltd., Sensor Technology Group, Imaging Division, Edinburgh, UK (GRID:grid.1006.7) 
773 0 |t Discover Electronics  |g vol. 2, no. 1 (Dec 2025), p. 42 
786 0 |d ProQuest  |t Engineering Database 
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