A Three Layer Lossless and Low Latency Network Protocol Stack Implemented Using FPGAs
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| Pubblicato in: | ProQuest Dissertations and Theses (2025) |
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ProQuest Dissertations & Theses
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| Accesso online: | Citation/Abstract Full Text - PDF |
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| Abstract: | As latency-sensitive services and applications increasingly populate data centers, performance often becomes limited by the high latency of network interconnects. The conventional network stack, designed for both LAN and WAN environments, incorporates substantial redundancy that is unnecessary for data center networks. This thesis presents the design and implementation of a three-layer network protocol stack, named RIFL Network, aimed at significantly reducing latency and enhancing throughput in data center networks and high-performance computing environments. The RIFL Network consists of the RIFL Link Layer, RIFL Switch, and RIFL Network Interface Controller. The RIFL Link Layer achieves extremely low latencies of 110 nanoseconds and supports scalability up to multi-hundred gigabits per second, addressing the high-throughput demands of modern data centers. The RIFL Switch employs a Batcher-Banyan network and an iSLIP scheduler to maintain intra-rack latency below 400 nanoseconds, effectively handling both Bernoulli and bursty traffic patterns within data centers. The RIFL NIC integrates an ultra-low latency PCIe DMA engine, EasyDMA, which minimizes CPU involvement and supports extensive virtualization capabilities. EasyDMA's architecture enables FPGA-CPU-FPGA round-trip communications as fast as 2.3 microseconds, supporting over 100 Gbps operations. Together, the RIFL Network provides high throughput, low latency, and lossless transmission, optimized for data center environments. |
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| ISBN: | 9798265437785 |
| Fonte: | ProQuest Dissertations & Theses Global |