High-Speed Architecture for Hybrid Arithmetic–Huffman Data Compression
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| Publicado en: | Technologies vol. 13, no. 12 (2025), p. 585-607 |
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| Autor principal: | |
| Publicado: |
MDPI AG
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| Materias: | |
| Acceso en línea: | Citation/Abstract Full Text + Graphics Full Text - PDF |
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| 024 | 7 | |a 10.3390/technologies13120585 |2 doi | |
| 035 | |a 3286357368 | ||
| 045 | 2 | |b d20250101 |b d20251231 | |
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| 100 | 1 | |a Wiseman Yair | |
| 245 | 1 | |a High-Speed Architecture for Hybrid Arithmetic–Huffman Data Compression | |
| 260 | |b MDPI AG |c 2025 | ||
| 513 | |a Journal Article | ||
| 520 | 3 | |a This paper proposes a hardware–software co-design for adaptive lossless compression based on Hybrid Arithmetic–Huffman Coding, a table-driven approximation of arithmetic coding that preserves near-optimal compression efficiency while eliminating the multiplicative precision and sequential bottlenecks that have traditionally prevented arithmetic coding deployment in resource-constrained embedded systems. The compression pipeline is partitioned as follows: flexible software on the processor core dynamically builds and adapts the prefix coding (usually Huffman Coding) frontend for accurate probability estimation and binarization; the resulting binary stream is fed to a deeply pipelined systolic hardware accelerator that performs binary arithmetic coding using pre-calibrated finite state transition tables, dedicated renormalization logic, and carry propagation mitigation circuitry instantiated in on-chip memory. The resulting implementation achieves compression ratios consistently within 0.4% of the theoretical entropy limit, multi-gigabit per second throughput in 28 nm/FinFET nodes, and approximately 68% lower energy per compressed byte than optimized software arithmetic coding, making it ideally suited for real-time embedded vision, IoT sensor networks, and edge multimedia applications. | |
| 653 | |a Huffman codes | ||
| 653 | |a Software | ||
| 653 | |a Mathematical analysis | ||
| 653 | |a Semiconductors | ||
| 653 | |a Hardware | ||
| 653 | |a Binary codes | ||
| 653 | |a Microprocessors | ||
| 653 | |a Real time | ||
| 653 | |a Architecture | ||
| 653 | |a Codes | ||
| 653 | |a Circuits | ||
| 653 | |a Research & development--R&D | ||
| 653 | |a Workloads | ||
| 653 | |a Compression ratio | ||
| 653 | |a Entropy | ||
| 653 | |a Data compression | ||
| 653 | |a Chips (memory devices) | ||
| 653 | |a Efficiency | ||
| 653 | |a Co-design | ||
| 653 | |a Design | ||
| 653 | |a Probability | ||
| 653 | |a Arithmetic coding | ||
| 653 | |a Embedded systems | ||
| 773 | 0 | |t Technologies |g vol. 13, no. 12 (2025), p. 585-607 | |
| 786 | 0 | |d ProQuest |t Materials Science Database | |
| 856 | 4 | 1 | |3 Citation/Abstract |u https://www.proquest.com/docview/3286357368/abstract/embedded/7BTGNMKEMPT1V9Z2?source=fedsrch |
| 856 | 4 | 0 | |3 Full Text + Graphics |u https://www.proquest.com/docview/3286357368/fulltextwithgraphics/embedded/7BTGNMKEMPT1V9Z2?source=fedsrch |
| 856 | 4 | 0 | |3 Full Text - PDF |u https://www.proquest.com/docview/3286357368/fulltextPDF/embedded/7BTGNMKEMPT1V9Z2?source=fedsrch |