Pharaoh Chip Compiler: 10-Week Wrap-Up
保存先:
| 出版年: | ESD vol. 18, no. 11 (Nov 1988), p. 48-52 |
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Digital Design Publishing
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| オンライン･アクセス: | Citation/Abstract Full Text - PDF |
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| 抄録: | Evans & Sutherland Computer Corp. (Salt Lake City, Utah) has introduced a 3-dimensional graphics/imaging subsystem with photographic-quality output. The subsystem determines the color of each object, decides which portions of which objects are visible, and then computes the final pixel value for the output to produce a 1,024-pixel-square color image, with a wide variety of shading effects, in only a few seconds. An ASIC filter chip, code-named Pharaoh in honor of its pyramid-shaped algorithm, is integral to this subsystem. Pharaoh implements a general filtering algorithm, allowing it to compute the color of each pixel in an image based on a weighted summation of neighboring pixels. The overall graphics subsystem computes a raster image from a set of 3D polygons, which are derived from a mathematical model describing the surface of an object and the object's approximate shape. The final verification stage of the Pharaoh design consisted of design rule checking, extraction, netlist comparison, and back-annotated simulation. Pharaoh's development illustrates the feasibility of one person designing a 75,000-gate chip within 10 weeks of finalizing the algorithm and LISP model, using today's design tools and compiler technology. |
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| ISSN: | 0893-2565 0147-9245 |
| ソース: | ABI/INFORM Global |