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FPGA Tool Suite Adds Native Static Timing Analysis

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Vydáno v:Electronic Design vol. 53, no. 16 (Jul 21, 2005), p. 32.
Hlavní autor: Maliniak, David
Vydáno:
Endeavor Business Media
Témata:
Actel Corp TransEDA Agilent EEsof EDA CriticalBlue
United States > US
Design engineering
Software packages
Electronic design automation
Manyproducts
Integrated circuits
Automation
Product introduction
Operating systems
Design
Designers
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Abstrakt:TransEDA's Assertain is billed as a "verification closure-management tool." But it's also a way to derive metrics that can tell users when their verification process is truly complete. Assertain monitors, measures, and manages the verification process in one integrated environment.
ISSN:0013-4872
1944-9550
Zdroj:Science Database