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RVAM16: a low-cost multiple-ISA processor based on RISC-V and ARM Thumb

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Publicado en:Frontiers of Computer Science vol. 19, no. 1 (Jan 2025), p. 191103
Autor principal: Huang, Libo
Otros Autores: Zhang, Jing, Yang, Ling, Ma, Sheng, Wang, Yongwen, Cheng, Yuanhu
Publicado:
Springer Nature B.V.
Materias:
Embedded systems
RISC
Energy consumption
Hardware
Microprocessors
Energy efficiency
Compatible software
Codes
Optimization
Acceso en línea:Citation/Abstract
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Resumen:The rapid development of ISAs has brought the issue of software compatibility to the forefront in the embedded field. To address this challenge, one of the promising solutions is the adoption of a multiple-ISA processor that supports multiple different ISAs. However, due to constraints in cost and performance, the architecture of a multiple-ISA processor must be carefully optimized to meet the specific requirements of embedded systems. By exploring the RISC-V and ARM Thumb ISAs, this paper proposes RVAM16, which is an optimized multiple-ISA processor microarchitecture for embedded devices based on hardware binary translation technique. The results show that, when running non-native ARM Thumb programs, RVAM16 achieves a significant speedup of over 2.73× with less area and energy consumption compared to using hardware binary translation alone, reaching more than 70% of the performance of native RISC-V programs.
ISSN:2095-2228
2095-2236
1673-7350
1673-7466
DOI:10.1007/s11704-023-3239-x
Fuente:Advanced Technologies & Aerospace Database