Embedded Streaming Hardware Accelerators Interconnect Architectures and Latency Evaluation

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Bibliografski detalji
Izdano u:	Electronics vol. 14, no. 8 (2025), p. 1513
Glavni autor:	Cristian-Tiberius, Axinte
Daljnji autori:	Stan, Andrei, Vasile-Ion, Manta
Izdano:	MDPI AG
Teme:	Software Central processing units > CPUs Random access memory Computer architecture Hardware Communication Microprocessors Signal processing Neural networks Network latency Design Architecture Embedded systems Transmitters Block diagrams First in-first out protocols Field programmable gate arrays Resource utilization System on chip Energy consumption Accelerators Interfaces
Online pristup:	Citation/Abstract Full Text + Graphics Full Text - PDF
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