Model-Based Design of Contrast-Limited Histogram Equalization for Low-Complexity, High-Speed, and Low-Power Tone-Mapping Operation
保存先:
| 出版年: | Electronics vol. 14, no. 12 (2025), p. 2416-2440 |
|---|---|
| 第一著者: | |
| その他の著者: | , |
| 出版事項: |
MDPI AG
|
| 主題: | |
| オンライン･アクセス: | Citation/Abstract Full Text + Graphics Full Text - PDF |
| タグ: |
タグなし, このレコードへの初めてのタグを付けませんか!
|
| 抄録: | Imaging applications involving outdoor scenes and fast motion require sensing and processing of high-dynamic-range images at video rates. In turn, image signal processing pipelines that serve low-dynamic-range displays require tone mapping operators (TMOs). For high-speed and low-power applications with low-cost field-programmable gate arrays (FPGAs), global TMOs that employ contrast-limited histogram equalization prove ideal. To develop such TMOs, this work proposes a MATLAB–Simulink–Vivado design flow. A realized design capable of megapixel video rates using milliwatts of power requires only a fraction of the resources available in the lowest-cost Artix-7 device from Xilinx (now Advanced Micro Devices). Unlike histogram-based TMO approaches for nonlinear sensors in the literature, this work exploits Simulink modeling to reduce the total required FPGA memory by orders of magnitude with minimal impact on video output. After refactoring an approach from the literature that incorporates two subsystems (Base Histograms and Tone Mapping) to one incorporating four subsystems (Scene Histogram, Perceived Histogram, Tone Function, and Global Mapping), memory is exponentially reduced by introducing a fifth subsystem (Interpolation). As a crucial stepping stone between MATLAB algorithm abstraction and Vivado circuit realization, the Simulink modeling facilitated a bit-true design flow. |
|---|---|
| ISSN: | 2079-9292 |
| DOI: | 10.3390/electronics14122416 |
| ソース: | Advanced Technologies & Aerospace Database |