Imagen de Portada

Improved Real-Time SPGA Algorithm and Hardware Processing Architecture for Small UAVs

Guardado en:
Publicado en:Remote Sensing vol. 17, no. 13 (2025), p. 2232-2263
Autor principal: Wang, Huan
Otros Autores: Liu, Yunlong, Li, Yanlei, Li, Hang, Ge Xuyang, Jihao, Xin, Liang Xingdong
Publicado:
MDPI AG
Materias:
Accuracy
Constant false alarm rate
Algorithms
Unmanned aerial vehicles
Synthetic aperture radar
Energy efficiency
Miniature aircraft
Design
Error analysis
Phase error
Field programmable gate arrays
Digital signal processors
Radar imaging
Real time
Reconfiguration
Parameter estimation
Acceso en línea:Citation/Abstract
Full Text + Graphics
Full Text - PDF
Etiquetas: Agregar Etiqueta
Sin Etiquetas, Sea el primero en etiquetar este registro!
Resumen:Real-time Synthetic Aperture Radar (SAR) imaging for small Unmanned Aerial Vehicles (UAVs) has become a significant research focus. However, limitations in Size, Weight, and Power (SwaP) restrict the imaging quality and timeliness of small UAV-borne SAR, limiting its practical application. This paper presents a non-iterative real-time Feature Sub-image Based Stripmap Phase Gradient Autofocus (FSI-SPGA) algorithm. The FSI-SPGA algorithm combines 2D Constant False Alarm Rate (CFAR) for coarse point selection and spatial decorrelation for refined point selection. This approach enables the accurate extraction of high-quality scattering points. Using these points, the algorithm constructs a feature sub-image containing comprehensive phase error information and performs a non-iterative phase error estimation based on this sub-image. To address the multifunctional, low-power, and real-time requirements of small UAV SAR, we designed a highly efficient hybrid architecture. This architecture integrates dataflow reconfigurability and dynamic partial reconfiguration and is based on an ARM + FPGA platform. It is specifically tailored to the computational characteristics of the FSI-SPGA algorithm. The proposed scheme was assessed using data from a 6 kg small SAR system equipped with centimeter-level INS/GPS. For SAR images of size 4096 × 12,288, the FSI-SPGA algorithm demonstrated a 6 times improvement in processing efficiency compared to traditional methods while maintaining the same level of precision. The high-efficiency reconfigurable ARM + FPGA architecture processed the algorithm in 6.02 s, achieving 12 times the processing speed and three times the energy efficiency of a single low-power ARM platform. These results confirm the effectiveness of the proposed solution for enabling high-quality real-time SAR imaging under stringent SwaP constraints.
ISSN:2072-4292
DOI:10.3390/rs17132232
Fuente:Advanced Technologies & Aerospace Database