Cita APA (7a ed.)
Achyuth, G., Shah, Y. A., Vemuri, S. M., & (Ken), C. K. (2025). Hardware Accelerator Design by Using RT-Level Power Optimization Techniques on FPGA for Future AI Mobile Applications. Electronics. https://doi.org/10.3390/electronics14163317
Cita Chicago Style (17a ed.)
Achyuth, Gundrapally, Yatrik Ashish Shah, Sai Manohar Vemuri, y Choi Kyuwon (Ken). "Hardware Accelerator Design by Using RT-Level Power Optimization Techniques on FPGA for Future AI Mobile Applications." Electronics 2025. https://doi.org/10.3390/electronics14163317.
Cita MLA (9a ed.)
Achyuth, Gundrapally, et al. "Hardware Accelerator Design by Using RT-Level Power Optimization Techniques on FPGA for Future AI Mobile Applications." Electronics, 2025, https://doi.org/10.3390/electronics14163317.
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