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FPGA-Accelerated ESN with Chaos Training for Financial Time Series Prediction

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Publicado en:Machine Learning and Knowledge Extraction vol. 7, no. 4 (2025), p. 160-182
Autor Principal: Hassaan, Zeinab A
Outros autores: Yacoub, Mohammed H, Said, Lobna A
Publicado:
MDPI AG
Materias:
United States > US
Currency exchanges
Stock prices
Accuracy
Risk management
Deep learning
Datasets
Forecasting
Optimization
Field programmable gate arrays
Stock exchanges
Technology stocks
Time series
Dynamical systems
Investment strategy
Machine learning
Fourier transforms
American dollar
Foreign exchange rates
Securities markets
Neural networks
Effectiveness
Recurrent neural networks
Stochastic models
Sequences
Lorenz system
Algorithms
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Resumo:Improving financial time series forecasting presents challenges because models often struggle to identify diverse fault patterns in unseen data. This issue is critical in fintech, where accurate and reliable forecasting of financial data is essential for effective risk management and informed investment strategies. This work addresses these challenges by initializing the weights and biases of two proposed models, Gated Recurrent Units (GRUs) and the Echo State Network (ESN), with different chaotic sequences to enhance prediction accuracy and capabilities. We compare reservoir computing (RC) and recurrent neural network (RNN) models with and without the integration of chaotic systems, utilizing standard initialization. The models are validated on six different datasets, including the 500 largest publicly traded companies in the US (S&P500), the Irish Stock Exchange Quotient (ISEQ) dataset, the XAU and USD forex pair (XAU/USD), the USD and JPY forex pair with respect to the currency exchange rate (USD/JPY), Chinese daily stock prices, and the top 100 index of UK companies (FTSE 100). The ESN model, combined with the Lorenz system, achieves the lowest error among other models, reinforcing the effectiveness of chaos-trained models for prediction. The proposed ESN model, accelerated by the Kintex-Ultrascale KCU105 FPGA board, achieves a maximum frequency of <inline-formula>83.5</inline-formula> MHz and a power consumption of <inline-formula>0.677</inline-formula> W. The results of the hardware simulation align with MATLAB R2025b fixed-point analysis.
ISSN:2504-4990
DOI:10.3390/make7040160
Fonte:Advanced Technologies & Aerospace Database