ASIC verification software automates partitioning

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Detalles Bibliográficos
Publicado en:	Electronic Design vol. 49, no. 18 (Sep 3, 2001), p. 34.
Autor Principal:	Maliniak, David
Publicado:	Endeavor Business Media
Materias:	Synplicity Inc United States > US Electronic design automation Software packages Automation Product introduction Design Designers
Acceso en liña:	Citation/Abstract Full Text + Graphics Full Text - PDF
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Descripción
Resumo:	Earlier versions of Certify incorporated the ability to recognize gated clock tree structures in an ASIC and convert them to dock enables in an FPGA. In addition to the logic gate elements previously recognized in the clock tree, the tool can now detect clock trees with inferred and instantiated memories and latches, instantiated registers, shift registers, state machines, and counters. This eliminates the time-consuming task of manually converting gated-- clock elements.
ISSN:	0013-4872 1944-9550
Fonte:	Science Database