ASIC verification software automates partitioning
保存先:
| 出版年: | Electronic Design vol. 49, no. 18 (Sep 3, 2001), p. 34. |
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| 第一著者: | |
| 出版事項: |
Endeavor Business Media
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| 主題: | |
| オンライン･アクセス: | Citation/Abstract Full Text + Graphics Full Text - PDF |
| タグ: |
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| 抄録: | Earlier versions of Certify incorporated the ability to recognize gated clock tree structures in an ASIC and convert them to dock enables in an FPGA. In addition to the logic gate elements previously recognized in the clock tree, the tool can now detect clock trees with inferred and instantiated memories and latches, instantiated registers, shift registers, state machines, and counters. This eliminates the time-consuming task of manually converting gated-- clock elements. |
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| ISSN: | 0013-4872 1944-9550 |
| ソース: | Science Database |