ASIC Verification Technology Brings Bugs To Their Knees
में बचाया:
| में प्रकाशित: | Electronic Design (Jan 18, 2007), p. 30. |
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| मुख्य लेखक: | |
| प्रकाशित: |
Endeavor Business Media
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| विषय: | |
| ऑनलाइन पहुंच: | Citation/Abstract Full Text Full Text - PDF |
| टैग: |
कोई टैग नहीं, इस रिकॉर्ड को टैग करने वाले पहले व्यक्ति बनें!
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| सार: | To employ Total Recall technology, users would specify a block or full chip for debugging. All memory, logic, and associated circuitry is surrounded by control logic and stimulus. That stimulus is delayed by a specified number of clocks, and all assertions in the HDL are synthesized into the control logic. The design is then loaded into an FPGAbased prototyping board and run as though in emulation. |
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| आईएसएसएन: | 0013-4872 1944-9550 |
| स्रोत: | Science Database |