ASIC Verification Technology Brings Bugs To Their Knees

שמור ב:

מידע ביבליוגרפי
הוצא לאור ב:	Electronic Design (Jan 18, 2007), p. 30.
מחבר ראשי:	Maliniak, David
יצא לאור:	Endeavor Business Media
נושאים:	Synplicity Inc United States > US Design engineering Simulation Exports Prototypes Design
גישה מקוונת:	Citation/Abstract Full Text Full Text - PDF
תגים:	הוספת תג אין תגיות, היה/י הראשונ/ה לתייג את הרשומה!

תיאור
Resumen:	To employ Total Recall technology, users would specify a block or full chip for debugging. All memory, logic, and associated circuitry is surrounded by control logic and stimulus. That stimulus is delayed by a specified number of clocks, and all assertions in the HDL are synthesized into the control logic. The design is then loaded into an FPGAbased prototyping board and run as though in emulation.
ISSN:	0013-4872 1944-9550
Fuente:	Science Database