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Heuristics to minimize makespan of parallel batch processing machines

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Publié dans:The International Journal of Advanced Manufacturing Technology vol. 37, no. 9-10 (Jun 2008), p. 1005
Auteur principal: Damodaran, Purushothaman
Autres auteurs: Ping-Yu, Chang
Publié:
Springer Nature B.V.
Sujets:
Printed circuits
Production scheduling
Batch processing
Simulated annealing
Heuristic
Circuit boards
Accès en ligne:Citation/Abstract
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Résumé:Batch-processing machines can process several jobs simultaneously. These machines are commonly used to test Printed Circuit Boards (PCBs). The processing time and the dimensions of the PCB are given. Each batch is formed such that the total size of all the PCBs in the batch does not exceed the machine capacity. The batch processing time is equal to the longest processing time of all the PCBs in the batch. These batch processing machines are expensive and a bottleneck. Scheduling PCBs on these parallel batch processing machines to minimize their makespan is NP-hard. Consequently, we propose several heuristics. The performance of the proposed heuristics is compared to a simulated annealing approach and a commercial solver.
ISSN:0268-3768
1433-3015
DOI:10.1007/s00170-007-1042-8
Source:Engineering Database