Heuristics to minimize makespan of parallel batch processing machines
I tiakina i:
| I whakaputaina i: | The International Journal of Advanced Manufacturing Technology vol. 37, no. 9-10 (Jun 2008), p. 1005 |
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| Kaituhi matua: | |
| Ētahi atu kaituhi: | |
| I whakaputaina: |
Springer Nature B.V.
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| Ngā marau: | |
| Urunga tuihono: | Citation/Abstract Full Text - PDF |
| Ngā Tūtohu: |
Kāore He Tūtohu, Me noho koe te mea tuatahi ki te tūtohu i tēnei pūkete!
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| Whakarāpopotonga: | Batch-processing machines can process several jobs simultaneously. These machines are commonly used to test Printed Circuit Boards (PCBs). The processing time and the dimensions of the PCB are given. Each batch is formed such that the total size of all the PCBs in the batch does not exceed the machine capacity. The batch processing time is equal to the longest processing time of all the PCBs in the batch. These batch processing machines are expensive and a bottleneck. Scheduling PCBs on these parallel batch processing machines to minimize their makespan is NP-hard. Consequently, we propose several heuristics. The performance of the proposed heuristics is compared to a simulated annealing approach and a commercial solver. |
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| ISSN: | 0268-3768 1433-3015 |
| DOI: | 10.1007/s00170-007-1042-8 |
| Puna: | Engineering Database |