A High-Performance Quadruple-Node-Upset-Tolerant Latch Design and an Algorithm for Tolerance Verification of Hardened Latches

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Detaylı Bibliyografya
Yayımlandı:	Journal of Electronic Testing : (JETTA) vol. 40, no. 1 (Feb 2024), p. 45
Yazar:	Xu, Hui
Diğer Yazarlar:	Qin, Xuewei, Ma, Ruijun, Liu, Chaoming, Zhu, Shuo, Wang, Jun, Liang, Huaguo
Baskı/Yayın Bilgisi:	Springer Nature B.V.
Konular:	Soft errors Algorithms Verification Integrated circuits Delay Power consumption Reliability Fault tolerance Tools Nodes Latches
Online Erişim:	Citation/Abstract Full Text - PDF
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