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A High-Performance Quadruple-Node-Upset-Tolerant Latch Design and an Algorithm for Tolerance Verification of Hardened Latches

Furkejuvvon:
Publikašuvnnas:Journal of Electronic Testing : (JETTA) vol. 40, no. 1 (Feb 2024), p. 45
Váldodahkki: Xu, Hui
Eará dahkkit: Qin, Xuewei, Ma, Ruijun, Liu, Chaoming, Zhu, Shuo, Wang, Jun, Liang, Huaguo
Almmustuhtton:
Springer Nature B.V.
Fáttát:
Soft errors
Algorithms
Verification
Integrated circuits
Delay
Power consumption
Reliability
Fault tolerance
Tools
Nodes
Latches
Liŋkkat:Citation/Abstract
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