Implementation of Systolic Multiplier Using Hybrid Multiplexer Dependent Adder
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| 出版年: | Turkish Journal of Computer and Mathematics Education vol. 15, no. 1 (2024), p. 218 |
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| 第一著者: | |
| その他の著者: | , , , |
| 出版事項: |
Ninety Nine Publication
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| オンライン･アクセス: | Citation/Abstract Full Text - PDF |
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| 抄録: | Multipliers are basic building blocks in various integrated circuits like microprocessors, micro controllers, and ALUs. The existing multipliers suffer from high power consumption and inefficient use of hardware resources. They often rely on traditional adder structures that are not tailored for specific operations, leading to suboptimal performance. Additionally, their fixed architectures limit adaptability and scalability in different applications. So, the proposed approach offers enhanced computational efficiency and reduced power consumption compared to conventional multiplier designs. By integrating multiplexer-dependent adders into the systolic array, the proposed method optimizes resource utilization and delivers improved performance for various arithmetic operations. This integration allows for dynamic selection of adder types based on the specific multiplication operation, significantly reducing power consumption and latency. By adapting the hardware resources to computational needs, the method achieves higher efficiency and flexibility, making it suitable for a wide range of applications in digital signal processing and data processing systems. |
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| ISSN: | 1309-4653 |
| ソース: | Science Database |