Imagen de Portada

DMR-SCL: A Design and Verification Framework for Redundancy-Based Resilient Asynchronous Sleep Convention Logic Circuits

Guardado en:
Publicado en:Electronics vol. 14, no. 5 (2025), p. 884
Autor principal: Datta, Mithun
Otros Autores: Mazumder, Dipayan, Bodoh, Alexander C, Sakib, Ashiq A
Publicado:
MDPI AG
Materias:
Null convention logic
Logic circuits
Sleep
Verification
Integrated circuits
Boolean
Latch-up
Radiation effects
Electromagnetic interference
Circuits
Design
Errors
Registration
Single Event Effects
Radiation
Benchmarks
Redundancy
Single event upsets
Acceso en línea:Citation/Abstract
Full Text + Graphics
Full Text - PDF
Etiquetas: Agregar Etiqueta
Sin Etiquetas, Sea el primero en etiquetar este registro!
Resumen:The digital integrated circuit (IC) design industry is continuously evolving. However, the rapid advancements in technology are accompanied by major reliability concerns. Conventional clock-based synchronous designs become exceedingly susceptible to transient errors, caused by radiation rays, power jitters, electromagnetic interferences (EMIs), and/or other noise sources, primarily due to aggressive device and voltage scaling. quasi-delay-insensitive (QDI) asynchronous (clockless) circuits demonstrate inherent robustness against such transient errors, owing to their unique architecture. However, they are not completely immune. This article presents a hardened QDI Sleep Convention Logic (SCL) asynchronous architecture, which can fully recover from radiation-induced single-event effects such as single-event upset (SEU) and single-event latch-up (SEL). Multiple benchmark circuits are designed based on the proposed architecture. The simulation results indicate that the proposed designs offer substantial energy savings per operation, dissipate substantially less power during idle phases, and have lower area footprints in comparison to designs based on an existing resilient Null Convention Logic (NCL) architecture at the cost of increased latency. In addition, a formal verification framework for the proposed architecture is also presented. The performance and scalability of the proposed verification scheme are demonstrated using several multiplier benchmark circuits of varying width.
ISSN:2079-9292
DOI:10.3390/electronics14050884
Fuente:Advanced Technologies & Aerospace Database