DMR-SCL: A Design and Verification Framework for Redundancy-Based Resilient Asynchronous Sleep Convention Logic Circuits
Guardado en:
| Publicado en: | Electronics vol. 14, no. 5 (2025), p. 884 |
|---|---|
| Autor principal: | |
| Otros Autores: | , , |
| Publicado: |
MDPI AG
|
| Materias: | |
| Acceso en línea: | Citation/Abstract Full Text + Graphics Full Text - PDF |
| Etiquetas: |
Sin Etiquetas, Sea el primero en etiquetar este registro!
|
MARC
| LEADER | 00000nab a2200000uu 4500 | ||
|---|---|---|---|
| 001 | 3176377897 | ||
| 003 | UK-CbPIL | ||
| 022 | |a 2079-9292 | ||
| 024 | 7 | |a 10.3390/electronics14050884 |2 doi | |
| 035 | |a 3176377897 | ||
| 045 | 2 | |b d20250101 |b d20251231 | |
| 084 | |a 231458 |2 nlm | ||
| 100 | 1 | |a Datta, Mithun |u Department of Electrical and Computer Engineering, Florida Polytechnic University, Lakeland, FL 33805, USA; <email>mdatta2164@floridapoly.edu</email> (M.D.); <email>dmazumder8582@floridapoly.edu</email> (D.M.); <email>abodoh8714@floridapoly.edu</email> (A.C.B.) | |
| 245 | 1 | |a DMR-SCL: A Design and Verification Framework for Redundancy-Based Resilient Asynchronous Sleep Convention Logic Circuits | |
| 260 | |b MDPI AG |c 2025 | ||
| 513 | |a Journal Article | ||
| 520 | 3 | |a The digital integrated circuit (IC) design industry is continuously evolving. However, the rapid advancements in technology are accompanied by major reliability concerns. Conventional clock-based synchronous designs become exceedingly susceptible to transient errors, caused by radiation rays, power jitters, electromagnetic interferences (EMIs), and/or other noise sources, primarily due to aggressive device and voltage scaling. quasi-delay-insensitive (QDI) asynchronous (clockless) circuits demonstrate inherent robustness against such transient errors, owing to their unique architecture. However, they are not completely immune. This article presents a hardened QDI Sleep Convention Logic (SCL) asynchronous architecture, which can fully recover from radiation-induced single-event effects such as single-event upset (SEU) and single-event latch-up (SEL). Multiple benchmark circuits are designed based on the proposed architecture. The simulation results indicate that the proposed designs offer substantial energy savings per operation, dissipate substantially less power during idle phases, and have lower area footprints in comparison to designs based on an existing resilient Null Convention Logic (NCL) architecture at the cost of increased latency. In addition, a formal verification framework for the proposed architecture is also presented. The performance and scalability of the proposed verification scheme are demonstrated using several multiplier benchmark circuits of varying width. | |
| 653 | |a Null convention logic | ||
| 653 | |a Logic circuits | ||
| 653 | |a Sleep | ||
| 653 | |a Verification | ||
| 653 | |a Integrated circuits | ||
| 653 | |a Boolean | ||
| 653 | |a Latch-up | ||
| 653 | |a Radiation effects | ||
| 653 | |a Electromagnetic interference | ||
| 653 | |a Circuits | ||
| 653 | |a Design | ||
| 653 | |a Errors | ||
| 653 | |a Registration | ||
| 653 | |a Single Event Effects | ||
| 653 | |a Radiation | ||
| 653 | |a Benchmarks | ||
| 653 | |a Redundancy | ||
| 653 | |a Single event upsets | ||
| 700 | 1 | |a Mazumder, Dipayan |u Department of Electrical and Computer Engineering, Florida Polytechnic University, Lakeland, FL 33805, USA; <email>mdatta2164@floridapoly.edu</email> (M.D.); <email>dmazumder8582@floridapoly.edu</email> (D.M.); <email>abodoh8714@floridapoly.edu</email> (A.C.B.) | |
| 700 | 1 | |a Bodoh, Alexander C |u Department of Electrical and Computer Engineering, Florida Polytechnic University, Lakeland, FL 33805, USA; <email>mdatta2164@floridapoly.edu</email> (M.D.); <email>dmazumder8582@floridapoly.edu</email> (D.M.); <email>abodoh8714@floridapoly.edu</email> (A.C.B.) | |
| 700 | 1 | |a Sakib, Ashiq A |u Department of Electrical and Computer Engineering, Southern Illinois University Edwardsville, Edwardsville, IL 62026, USA | |
| 773 | 0 | |t Electronics |g vol. 14, no. 5 (2025), p. 884 | |
| 786 | 0 | |d ProQuest |t Advanced Technologies & Aerospace Database | |
| 856 | 4 | 1 | |3 Citation/Abstract |u https://www.proquest.com/docview/3176377897/abstract/embedded/7BTGNMKEMPT1V9Z2?source=fedsrch |
| 856 | 4 | 0 | |3 Full Text + Graphics |u https://www.proquest.com/docview/3176377897/fulltextwithgraphics/embedded/7BTGNMKEMPT1V9Z2?source=fedsrch |
| 856 | 4 | 0 | |3 Full Text - PDF |u https://www.proquest.com/docview/3176377897/fulltextPDF/embedded/7BTGNMKEMPT1V9Z2?source=fedsrch |