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Verification methods for complex-functional blocks in CAD for chips deep submicron design standards

Enregistré dans:
Publié dans:E3S Web of Conferences vol. 376 (2023), p. n/a
Auteur principal: Zolnikov, Vladimir
Autres auteurs: Zolnikov, Konstantin, Ilina, Nadezhda, Grabovy, Kirill
Publié:
EDP Sciences
Sujets:
Russia
Very large scale integration
Design standards
Verification
Circuit design
Integrated circuits
Software
Semiconductors
Environmental
Accès en ligne:Citation/Abstract
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Résumé:The article discusses the design stages of very large-scale integrated circuits (VLSI) and the features of the procedure for verifying complex-functional VLSI blocks. The main approaches to microcircuit verification procedures are analyzed to minimize the duration of verification cycles. In practice, a combination of several approaches to verification is usually used.
ISSN:2555-0403
2267-1242
DOI:10.1051/e3sconf/202337601090
Source:Engineering Database