Нүүр зураг

FPGA Tool Suite Adds Native Static Timing Analysis

-д хадгалсан:
-д хэвлэсэн:Electronic Design vol. 53, no. 16 (Jul 21, 2005), p. 32.
Үндсэн зохиолч: Maliniak, David
Хэвлэсэн:
Endeavor Business Media
Нөхцлүүд:
Actel Corp TransEDA Agilent EEsof EDA CriticalBlue
United States > US
Design engineering
Software packages
Electronic design automation
Manyproducts
Integrated circuits
Automation
Product introduction
Operating systems
Design
Designers
Онлайн хандалт:Citation/Abstract
Full Text + Graphics
Full Text - PDF
Шошгууд: Шошго нэмэх
Шошго байхгүй, Энэхүү баримтыг шошголох эхний хүн болох!
Хураангуй:TransEDA's Assertain is billed as a "verification closure-management tool." But it's also a way to derive metrics that can tell users when their verification process is truly complete. Assertain monitors, measures, and manages the verification process in one integrated environment.
ISSN:0013-4872
1944-9550
Эх сурвалж:Science Database