FPGA Tool Suite Adds Native Static Timing Analysis
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| Publicado no: | Electronic Design vol. 53, no. 16 (Jul 21, 2005), p. 32. |
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| Autor principal: | |
| Publicado em: |
Endeavor Business Media
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| Assuntos: | |
| Acesso em linha: | Citation/Abstract Full Text + Graphics Full Text - PDF |
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| Resumo: | TransEDA's Assertain is billed as a "verification closure-management tool." But it's also a way to derive metrics that can tell users when their verification process is truly complete. Assertain monitors, measures, and manages the verification process in one integrated environment. |
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| ISSN: | 0013-4872 1944-9550 |
| Fonte: | Science Database |