ASIC Verification Technology Brings Bugs To Their Knees

Αποθηκεύτηκε σε:

Λεπτομέρειες βιβλιογραφικής εγγραφής
Εκδόθηκε σε:	Electronic Design (Jan 18, 2007), p. 30.
Κύριος συγγραφέας:	Maliniak, David
Έκδοση:	Endeavor Business Media
Θέματα:	Synplicity Inc United States > US Design engineering Simulation Exports Prototypes Design
Διαθέσιμο Online:	Citation/Abstract Full Text Full Text - PDF
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Περιγραφή
Περίληψη:	To employ Total Recall technology, users would specify a block or full chip for debugging. All memory, logic, and associated circuitry is surrounded by control logic and stimulus. That stimulus is delayed by a specified number of clocks, and all assertions in the HDL are synthesized into the control logic. The design is then loaded into an FPGAbased prototyping board and run as though in emulation.
ISSN:	0013-4872 1944-9550
Πηγή:	Science Database