A Novel Reconfigurable Vector-Processed Interleaving Algorithm for a DVB-RCS2 Turbo Encoder

Wedi'i Gadw mewn:

Manylion Llyfryddiaeth
Cyhoeddwyd yn:	Electronics vol. 14, no. 13 (2025), p. 2600-2617
Prif Awdur:	Bensimon Moshe
Awduron Eraill:	Boxerman Ohad, Ben-Shimol Yehuda, Manor Erez, Greenberg, Shlomo
Cyhoeddwyd:	MDPI AG
Pynciau:	Wireless communications Channel capacity Satellite communications Hardware Error correction Turbo codes Architecture Data transmission Codes Coders Efficiency Data integrity Embedded systems Error correction & detection Digital video Communications systems Algorithms Vector processing (computers) Data storage Modular structures Permutations Real time Array processors
Mynediad Ar-lein:	Citation/Abstract Full Text + Graphics Full Text - PDF
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