A Novel Reconfigurable Vector-Processed Interleaving Algorithm for a DVB-RCS2 Turbo Encoder

Gardado en:

Detalles Bibliográficos
Publicado en:	Electronics vol. 14, no. 13 (2025), p. 2600-2617
Autor Principal:	Bensimon Moshe
Outros autores:	Boxerman Ohad, Ben-Shimol Yehuda, Manor Erez, Greenberg, Shlomo
Publicado:	MDPI AG
Materias:	Wireless communications Channel capacity Satellite communications Hardware Error correction Turbo codes Architecture Data transmission Codes Coders Efficiency Data integrity Embedded systems Error correction & detection Digital video Communications systems Algorithms Vector processing (computers) Data storage Modular structures Permutations Real time Array processors
Acceso en liña:	Citation/Abstract Full Text + Graphics Full Text - PDF
Etiquetas:	Engadir etiqueta Sen Etiquetas, Sexa o primeiro en etiquetar este rexistro!

Sexa o primeiro en deixar un comentario!