Hardware Accelerator Design by Using RT-Level Power Optimization Techniques on FPGA for Future AI Mobile Applications

Wedi'i Gadw mewn:

Manylion Llyfryddiaeth
Cyhoeddwyd yn:	Electronics vol. 14, no. 16 (2025), p. 3317-3329
Prif Awdur:	Achyuth, Gundrapally
Awduron Eraill:	Shah, Yatrik Ashish, Vemuri, Sai Manohar, Choi Kyuwon (Ken)
Cyhoeddwyd:	MDPI AG
Pynciau:	Xilinx Inc Electric vehicles Applications programs Optimization techniques Artificial neural networks Optimization Mobile computing Mathematical functions Power management Unmanned aerial vehicles Field programmable gate arrays Object recognition Python Real time Constraints Surveillance systems Design techniques Efficiency
Mynediad Ar-lein:	Citation/Abstract Full Text + Graphics Full Text - PDF
Tagiau:	Ychwanegu Tag Dim Tagiau, Byddwch y cyntaf i dagio'r cofnod hwn!

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