Hardware Accelerator Design by Using RT-Level Power Optimization Techniques on FPGA for Future AI Mobile Applications

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Dettagli Bibliografici
Pubblicato in:	Electronics vol. 14, no. 16 (2025), p. 3317-3329
Autore principale:	Achyuth, Gundrapally
Altri autori:	Shah, Yatrik Ashish, Vemuri, Sai Manohar, Choi Kyuwon (Ken)
Pubblicazione:	MDPI AG
Soggetti:	Xilinx Inc Electric vehicles Applications programs Optimization techniques Artificial neural networks Optimization Mobile computing Mathematical functions Power management Unmanned aerial vehicles Field programmable gate arrays Object recognition Python Real time Constraints Surveillance systems Design techniques Efficiency
Accesso online:	Citation/Abstract Full Text + Graphics Full Text - PDF
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