Hardware Accelerator Design by Using RT-Level Power Optimization Techniques on FPGA for Future AI Mobile Applications

Guardado en:

書目詳細資料
發表在:	Electronics vol. 14, no. 16 (2025), p. 3317-3329
主要作者:	Achyuth, Gundrapally
其他作者:	Shah, Yatrik Ashish, Vemuri, Sai Manohar, Choi Kyuwon (Ken)
出版:	MDPI AG
主題:	Xilinx Inc Electric vehicles Applications programs Optimization techniques Artificial neural networks Optimization Mobile computing Mathematical functions Power management Unmanned aerial vehicles Field programmable gate arrays Object recognition Python Real time Constraints Surveillance systems Design techniques Efficiency
在線閱讀:	Citation/Abstract Full Text + Graphics Full Text - PDF
標簽:	添加標簽沒有標簽, 成為第一個標記此記錄!

成為第一個發表評論!